Toshiba Smart Gate Driver Coupler DESAT Detection Circuit Design Guide

When using Smart Gate Driver (SGD) couplers such as the TLP5214A, TLP5214, TLP5212, and TLP5222, designing the peripheral circuit effectively is crucial for utilizing the VCE(sat) detection function. VCE(sat) detection, also known as DESAT detection, is a protection mechanism designed to detect a rise in the collector or drain voltage when an overcurrent occurs in power semiconductor switching devices (such as IGBTs, Si- or SiC-MOSFETs, GaN-FETs), and to trigger a shutdown signal to protect the device.

During the design process, factors such as load inductance, noise generated from switching in other phases, or electromagnetic induction can cause false detection in the DESAT detection circuit. To reduce the likelihood of such false detection, a series of design recommendations are provided.

In the design of the DESAT detection circuit, when the collector or drain voltage of the power device exceeds the preset VDESAT value, the SGD coupler stops driving the power device and outputs a fault signal from the FAULT_N terminal. For example, when using the TLP5214A to drive an IGBT, if the IGBT is turned on (VOUT is high), the DESAT terminal sources an ICHG current. CBLANK charges through RDESAT and DDESAT, but due to IGBT saturation, CBLANK does not charge up to the DESAT threshold voltage VDESAT. If the IGBT's VCE rises due to overcurrent, CBLANK begins to charge. Once the DESAT terminal voltage exceeds VDESAT, the SGD coupler detects the IGBT's DESAT condition and outputs a FAULT_N signal. This is illustrated in Figure 1.1.

Noise Infiltration Path Issues

Due to the distance between the power device and the SGD coupler, the connecting traces can introduce electromagnetic interference (EMI). In multi-phase inverter applications, switching from other phases may introduce noise through parasitic capacitance, potentially leading to false DESAT detection. Therefore, it is recommended to avoid routing the DESAT detection traces adjacent to traces carrying high-current pulses or traces connected to nodes with large potential fluctuations during PCB layout. Furthermore, placing RDESAT, DDESAT, and CBLANK as close as possible to the SGD coupler maximizes the low-pass filtering effect.

Determining DESAT Detection Circuit Constants
Guidance is provided regarding the values for CBLANK and RDESAT, as well as how to select DDESAT. If the desired blanking time (tBLANK) is set to 5 microseconds, and the standard ICHG value for the TLP5214A is 240 microamperes, then CBLANK should be selected to be approximately 200 picofarads.